1. Field of the Invention
The present invention relates to a semiconductor device (e.g., a complementary circuit) comprising an n-channel transistor and a p-channel transistor.
2. Description of the Related Art
Japanese Unexamined Patent Publication (Kokai) No. 57-7165 filed on June 17, 1980, by the present inventor, disclosed a high speed semiconductor device having a heterojunction formed between two semiconductor layers having different electron affinities, e.g., a gallium arsenide (GaAs) layer and an aluminum gallium arsenide (AlGaAs) layer, and using a two-dimensional gas layer (i.e., an electron accumulating layer) generated at the heterojunction interface. In this semiconductor device a control electrode corresponding to a gate electrode and controlling an electron density of the two-dimensional layer is formed on the AlGaAs electron supply layer. The impedance of the two-dimensional layer in the GaAs layer between a source electrode and a drain electrode can be varied by a voltage applied to the control electrode.
In the above-mentioned semiconductor device, however, since the AlGaAs layer is a semiconductor having a small electron affinity, i.e., a large energy gap, contains donor impurities (i.e., the AlGaAs layer has n-type conductivity), the donor impurities diffuse into the GaAs layer, which is a semiconductor having a large electron affinity, i.e., a small energy gap. Thus, the diffused impurities hinder the improvement of the electron mobility of the two-dimensional electron gas layer.
To overcome the above-mentioned disadvantage of the semiconductor device, in Japanese Unexamined Patent Publication (Kokai) No. 58-51574, filed on Sept. 22, 1981, the present inventor proposed to insert a buffer layer of undoped AlGaAs between the GaAs layer and the n-type GaAs layer. Such an improved semiconductor device is illustrated in FIG. 1. The semiconductor device comprises a semi-insulating GaAs substrate 1, an i-type GaAs channel layer 2, an i-type AlGaAs buffer layer 3, an n-type GaAs control layer 4, a control electrode (gate electrode) 5, an n.sup.+ -type source region 6, an n.sup.+ -type drain region 7, a source electrode 8, and a drain electrode 9. In this case, since the energy gap of the control layer 4 must be not more than that of the i-type GaAs channel layer 2, GaAs is selected for the material of the control layer 4. The material, impurity density, and thickness of the control layer 4 are adjusted to the optimum conditions to bring the surface potential of the GaAs channel layer 2 at the interface between the GaAs channel layer 2 and the i-type AlGaAs buffer layer 3 to 0 volt under thermal equilibrium conditions. When a positive voltage is applied to the control electrode 5, a two-dimensional electron gas layer (electron accumulating layer) 10 is generated in the channel layer 2 near the heterojunction interface, as shown in FIG. 1. The two-dimensional electron gas layer 10 serves as a channel below the control (gate) electrode 5, and thus the semiconductor device operates at a high speed in an enhancement-mode.
To increase the performance of an integrated circuit, it is important to decrease the power consumption thereof in addition to increasing the operating speed. To this end, in Japanese Unexamined Patent Publication (Kokai) No. 58-147167 filed on Feb. 26, 1982, the present inventor proposed a complementary semiconductor device comprising an n-channel transistor utilizing a two-dimensional electron gas and a p-channel transistor utilizing a two-dimensional hole gas. In this case, since either an n-type AlGaAs electron supply layer or a p-type AlGaAs hole supply layer is not sequentially formed on a GaAs channel layer, a heterojunction between the channel layer and the n-type AlGaAs layer or the p-type AlGaAs layer does not reach a sufficient level of excellence.